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[VHDL-FPGA-Verilog] modelsim_guide_cn

Description: 使用ModelSim进行设计仿真ModelSim为HDL仿真工具，我们可以利用该软件来实现对所设计的VHDL或Verilog程序进行仿真，支持IEEE常见的各种硬件描述语言标准。可以进行两种语言的混合仿真，但推荐大家只对一种语言仿真。ModelSim常见的版本分为ModelSim XE和ModelSim SE两种，ModelSim版本更新很快-Design simulation using ModelSim HDL simulator ModelSim is, we can use the software to achieve the program designed to simulate VHDL or Verilog, to support a variety of common IEEE standard hardware description language. Mixture of two languages ​ ​ can be simulated, but recommend only one language simulation. Common version of ModelSim and ModelSim SE ModelSim XE is divided into two types, ModelSim version update soon
Platform: | Size: 342016 | Author: 谢明 | Hits:

[VHDL-FPGA-Verilog] honglvdeng

Description: Verilog HDL作为一种规范的硬件描述语言,被广泛应用于电路的设计中。他的设计描述可被不同的工具所支持,可用不同器件来实现。利用Verilog HDL语言自顶向下的设计方法设计交通灯控制系统，使其实现道路交通的正常运转，突出了其作为硬件描述语言的良好的可读性、可移植性和易理解等优点，并通过Xilinx ISE6.02和ModelSim5.6完成综合、仿真。此程序通过下载到FPGA芯片后,可应用于实际的交通灯控制系统中。-Verilog HDL as a standard hardware description language, is widely used in circuit design. Description of his design can be supported by different tools, different devices can be used to achieve. Using Verilog HDL language top-down design approach traffic light control system to achieve the normal operation of road transport, highlighting its good as a hardware description language, readability, portability and ease of understanding, etc., and completed by Xilinx ISE6.02 and ModelSim5.6 synthesis, simulation. Through this program downloaded to the FPGA chip, can be applied to the actual traffic light control system.
Platform: | Size: 1024 | Author: zhaomin | Hits:

[VHDL-FPGA-Verilog] PS2_01

Description: 进阶实验_08_PS2_01 接受标准键盘输入，通过串口打印到PC，verilog-Advanced experimental _08_PS2_01 acceptable standard keyboard input through serial port to print to PC, verilog
Platform: | Size: 670720 | Author: 林爻 | Hits:

[VHDL-FPGA-Verilog] i2cslave_latest.tar

Description: I2C从机控制器Verilog源码，实现标准I2C从机接口-I2C slave controller Verilog source code to achieve the standard I2C slave interface
Platform: | Size: 1296384 | Author: CL | Hits:

[VHDL-FPGA-Verilog] lizi

Description: 用标准的verilog实现的vga256色，实验，可以在电脑上是实现，用的就是家用的电脑显示器，可以清楚看到256se-this is a standard verilog experence which can dest the vga 256 color
Platform: | Size: 327680 | Author: 宋俊福 | Hits:

[VHDL-FPGA-Verilog] floating_point_multiplier_verilog

Description: This code has written in verilog and it can multiply two floating point number with IEEE 754 standards and the out put of this code is in IEEE 754 standard.We have to put input in binary and the out put is also in binary.
Platform: | Size: 1024 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] frac_divider_verilog

Description: This code has written in verilog and it can divide two fraction numbers in fixed point standard .In this code ni shows the number of bits of inputs and no shows the number of bits of output and if we want more precision we can change this parameters and we get more accuracy.
Platform: | Size: 1024 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] MY-DDS

Description: 利用altera公司的FPGA使用verilog语言实现DDS功能 外加DA 可将数字信号转换成标准正弦信号-Altera FPGA use verilog language of DDS functions plus DA converts digital signals into a standard sine signal
Platform: | Size: 1305600 | Author: 李枫 | Hits:

[VHDL-FPGA-Verilog] My_DES3

Description: a triple-DES (Data Encryption Standard) hardware description in verilog-HDL with testbench
Platform: | Size: 861184 | Author: Farzad | Hits:

[VHDL-FPGA-Verilog] 8051

Description: 8051系列cpu用verilog编写的。-Verilog the compilation American standard encryption algorithm 8051 cpu hardware realizes contains the complete code and the test order.
Platform: | Size: 58368 | Author: wu liang | Hits:

[VHDL-FPGA-Verilog] jtag_master_latest.tar

Description: jtag 主机,根据jtag 标准协议编写的verilog代码-the jtag host, according to the jtag standard agreement prepared by the verilog code
Platform: | Size: 3072 | Author: gzh | Hits:

[Special Effects] Tu767sim

Description: 一个用Verilog HDL编的656标准图像外同步仿真程序-Synchronous simulation program in a 656 series of standard images using Verilog HDL
Platform: | Size: 12288 | Author: youpeihan | Hits:

[VHDL-FPGA-Verilog] xapp495

Description: 居然没有找到verilog 这是xilinx的一个hdmi的标准核 我测试使用通过-Actually did not find verilog xilinx an hdmi standard nuclear my test use by
Platform: | Size: 49152 | Author: 玉凤 | Hits:

[VHDL-FPGA-Verilog] SHA_1_V

Description: 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL implementation
Platform: | Size: 3072 | Author: pppp | Hits:

[VHDL-FPGA-Verilog] SHA-256

Description: 基于FIPS 180-4标准的SHA-256算法的verilog HDL实现-SHA-256 algorithm based on FIPS 180-4 standard verilog HDL implementation
Platform: | Size: 4096 | Author: pppp | Hits:

[VHDL-FPGA-Verilog] sha1_v01

Description: 基于FIPS 180-4标准的SHA-1算法的verilog HDL实现，分模块分别实现-FIPS 180-4 standard SHA-1 algorithm-based verilog HDL sub-modules, respectively, to achieve
Platform: | Size: 6144 | Author: pppp | Hits:

[VHDL-FPGA-Verilog] rc_flt

Description: 基于FPGA实现的64阶升余弦FIR并行滤波器，采用iso18000.6c标准实现，具有很好的低通滤波效果，已通过后仿上板验证，采用verilog语言实现。-64 order raised cosine FIR FPGA-based parallel filters, implemented using iso18000.6c standard with a low-pass filtering effect imitation on the board has passed validation, using verilog language.
Platform: | Size: 4096 | Author: 小梦 | Hits:

[Post-TeleCom sofeware systems] newViterbi217

Description: 基于IEEE802.11n标准,采用verilog语言设计的(2,1,7)卷积码viterbi译码器,支持1/2,2/3,3/4,5/6四种码率的译码,以测试无误-IEEE802.11n standard Verilog language design (2,1,7) convolutional code viterbi decoder support 1/2, 2/3, 3/4, 5/6 four bit rate decoding to test and correct
Platform: | Size: 18432 | Author: logic | Hits:

[Modem program] fft3780

Description: DTMB GB20600-2006 中国地面数字电视标准 3780点IFFT verilog 源代码-DTMB GB20600-2006 terrestrial digital TV standard 3780-point IFFT verilog source code
Platform: | Size: 381952 | Author: bowei | Hits:

[Communication-Mobile] ethmac10_100M

Description: 以太网IP Core 它实现10/100 Mbps的MAC控制器功能。它是在IEEE802.3和802.3u 标准下设计实现的。-The Ethernet IP Core is a 10/100 Media Access Controller (MAC). It consists of a synthesizable Verilog RTL core that provides all features necessary to implement the Layer 2 protocol of the Ethernet standard. It is designed to run according to the IEEE 802.3 and 802.3u specifications that define the 10 Mbps and 100 Mbps Ethernet standards, respectively.
Platform: | Size: 18925568 | Author: haizi | Hits:
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